1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having an output driver with a variable swing capability.
2. Description of Related Art
Recently, synchronous memories that operate in synchronization with clock signal are widely used as main memories for personal computers or the like. According to one of the synchronous memories, that is, a DDR (Double Data Rate) synchronous memory, input/output data needs to be accurately in synchronization with external clock signal. Therefore, it is essential to provide a DLL (Delay Locked Loop) circuit that generates internal clock signal in synchronization with external clock signal (see Japanese Patent Application Laid-open No. 2007-116574).
The DLL circuit includes a replica driver that is a replica of an output driver and functions to monitor a phase of a replica clock signal outputted from the replica driver to cause a phase of read data outputted from the output driver to coincide with a phase of the external clock signal.
The read data outputted from the output driver is supplied to a memory controller that is a chip different from a synchronous memory chip. Accordingly, the output driver needs to drive a load possessed by a transmission line that connects the synchronous memory to the memory controller. However, the load of the transmission line varies depending on used systems and is not necessarily uniform even within a same system. Therefore, for example, in a DDR3 synchronous memory, a swing capability of an output driver is made variable by changing a set value of a mode register, thereby maintaining a substantially fixed data slew rate.
However, when a swing capability of the output driver is changed, the time required from a transition start timing of the read data to when the read data reaches a threshold level (a boundary level between a high level and a low level) is also changed. That is, when the swing capability of the output driver is increased, the slew rate of outputted read data is also increased (that is, rise or fall of the read data becomes sharp). The time required from the transition start timing of the read data to when the read data reaches the threshold level is thus shortened. On the other hand, when the swing capability of the output driver is decreased, the slew rate of the outputted read data is also decreased (that is, rise or fall of the read data becomes gentle). The time required from the transition start timing of the read data to when the read data reaches the threshold level is thus extended.
Meanwhile, in conventional semiconductor devices, the swing capability of replica drivers is fixed. Therefore, when a swing capability of an output driver is changed, askew occurs in read data. Specifically, the timing when the read data exceeds a threshold level becomes earlier than a desired timing when the swing capability of the output driver is increased. On the other hand, when the swing capability of the output driver is decreased, the timing is delayed with respect to a desired timing.
Japanese Patent Application Laid-open No. 2007-116574 discloses a technique of changing a delay amount of replica clock signals based on a result of a calibration operation for adjusting an impedance of an output driver. However, measures against a case that a swing capability of the output driver is switched by changing a set value of the mode register are not disclosed. Furthermore, because the impedance adjustment based on a calibration operation is a fine adjustment operation for canceling changes in temperature and variations in voltage, the method described in Japanese Patent Application Laid-open No. 2007-116574 cannot deal with a case that output characteristics change greatly like when the swing capability of the output driver is changed. Further, the method described in Japanese Patent Application Laid-open No. 2007-116574 requires a variable delay circuit to be added to a clock tree through which a replica clock signal propagates. Therefore, the symmetry between the delay amount of a clock tree from a DLL circuit to the output driver (a normal tree) and the delay amount of a clock tree from the DLL circuit to a replica driver (a replica tree) is hardly ensured.
The problems described above are not specific problems of memory devices such as synchronous memories, but are common to semiconductor devices including an output driver with a variable swing capability.